IBM’s next Z processor natively supports ARM

IBM’s die shot shows the large Level-2 caches in the middle, with eleven CPU cores and a single AI unit alongside them. The upcoming Z processor is expected to natively run software for IBM’s z/Architecture and for ARM64. According to IBM, ARM is neither emulated nor handled by a coprocessor.

This addresses a longstanding bottleneck for mainframes: software no longer has to be adapted exclusively for z/Architecture. Linux can run in parallel for Z processors, or s390x, and for ARM64. Kernel-based virtual machines, or KVM for short, flexibly distribute computing workloads across the cores; switching between the two modes is expected to take one nanosecond. In the meantime, z/OS can continue running in its own partition on the same processor.

The key specifications are also changing. Compared with the Telum II, the number of cores rises from eight to eleven, while the base clock frequency increases from 5.5 GHz to at least 5.7 GHz. The Level-2 cache remains at 36 MByte per core, but the resulting virtual Level-3 cache grows to 432 MByte. The virtual Level-4 cache increases from just under 2.9 to 3.5 GByte. The chip is expected to be manufactured using a 2-nm process; IBM names Samsung as the likely manufacturer.

So what does this change in practice? Alongside traditional mainframe software, such as software for credit card transactions, operators will be able to run Linux applications for ARM64 on the same hardware without having to adapt them to z/Architecture. For IBM, this expands the range of potential applications without abandoning the operation of z/OS. So far, the promised seamlessness is based on IBM’s statements; no delivery date has been announced, nor has the performance of the AI unit.

IBM has not yet revealed the name of Telum II’s successor. The final clock speed is also still pending. The figures presented come from the announcement for the Hot Chips conference and therefore describe an upcoming processor, not an already available mainframe.