TSMC verifies backside power delivery while maintaining existing design in A16

Just as power lines and vehicles are forced into the same narrow street, power wiring and signal wiring share the front side of a miniaturized chip. To avoid this conflict, TSMC has developed and validated technology that moves the power delivery path to the back of the chip in its angstrom-class CMOS platform A16, Electronic Times reported on the 18th.

The key point is that the company moved the power grid without significantly disrupting the front side of the design. TSMC applied its “super power rail” approach to connect power to each transistor’s source and drain through dedicated contacts on the back of the chip. The company says it preserved the N2P process’s gate density and NanoFlex design flexibility by leaving the front-side gate structure, cell size and layout area largely unchanged.

Existing backside power technologies came with the burden of redesigning cell libraries and cell architectures in exchange for separating the power wiring. Electronic Times reported that Intel, which commercialized backside power delivery first, adjusted the number of fins, metal pitch and cell configuration during testing. TSMC’s approach is closer to changing the power delivery method while carrying forward more of the existing design assets.

In numerical terms, compared with N2P, speed can increase by 8–10% at the same power, or power consumption can decrease by 15–20% at the same speed. Chip density could also increase by 8–10%. This means the technology could target both performance and power efficiency in AI accelerators and high-performance computing chips, where signal paths are complex and power consumption is high, while reducing the burden of design changes. These figures are from TSMC’s development and validation results, and A16 mass production is scheduled to begin in the fourth quarter of this year.

What changes, then, is the design team’s time and range of options. If existing cells and design expertise can be used while sending the power grid to the back side, AI and high-performance computing chips will face less pressure to be redesigned from scratch as engineers seek to improve power efficiency.