NVIDIA GPU libraries speed chip simulation, early tests show

Before a single wafer moves through a new process step, a chip factory has to know whether that step will work. Increasingly, the answer comes from a simulation: a digital twin, a virtual copy of the process that engineers can change, test and rerun. NVIDIA announced that semiconductor companies are adopting its CUDA-X libraries, a set of accelerated software tools, to make these simulations faster and to let AI agents run them.

The bottleneck is computation. Modelling how atoms and molecules interact is central to materials research, and it can take a long time even on software already tuned for GPUs, the parallel processors that run many calculations at once. The new cuPotential library adds GPU-accelerated functions to existing programs, and in early-access testing it gave an extra 2–3x on workflows already optimised for GPUs. Synopsys reported a potential 30x speedup with cuEST in early QuantumATK results, and 12x with cuDSS on S-Device benchmarks.

Design-software companies are putting the same libraries under their own tools. Cadence reports that its AuraStack AI Super Agent optimised advanced packages for heat and stress 8x faster using cuDSS. COMSOL cites simulations up to 10x faster, with a planned MCP Server that will use an NVIDIA open model for AI-assisted design. Voltai says its Voltaire platform cuts the time for electro-thermal-mechanical workflows in 3D-IC design from months to a day. ChipAgents is working with NVIDIA on Build-A-Chip Bench, a benchmark meant to measure progress in automated chip engineering.

On the factory side, Imec uses NVIDIA tools to remove noise from scanning electron microscope images used for sub-nanometer measurements, and reports a 30% improvement in its lithography process window. Lam Research plans to integrate NanoVDB into its SEMulator3D platform, citing up to 30x on selected wafer-etch modelling tasks, and has demonstrated cutting plasma-prediction simulations from days to milliseconds with PhysicsNeMo. Luminary says engineers can evaluate 100x more package designs within the same schedule.

For a chip engineer, the gain is in the number of iterations: a test that once took days can run before a change reaches the line. Design-tool suppliers and their customers gain first, since Synopsys and Cadence already run these libraries in their products, while fab-side integrations such as Lam's are still described as plans or demonstrations. Whether the speedups hold on production lines, rather than in benchmarks, is the question the announcement does not answer.