QuickLogic expands GF 12LP eFPGA IP beyond 250,000 LUTs

A chip can leave manufacturing with a programmable block still inside it: QuickLogic has expanded its eFPGA hard IP for GF 12LP with a new DSP MAC unit, fabric scaling to more than 250,000 LUTs, and an optional configuration-bit health monitor.

An eFPGA, or embedded field-programmable gate array, places programmable logic directly in an SoC, or system-on-chip. QuickLogic says that allows critical hardware functions, algorithms and interfaces to be updated after manufacturing. Designers can choose combinations of look-up tables (LUTs), BlockRAM memory and digital signal processing (DSP) resources, with Aurora and AuroraPRO supporting the RTL-to-bitstream development flow.

The new DSP multiply-and-accumulate (MAC) unit adds an enhanced preadder, cascade connections and SIMD, or single-instruction, multiple-data, functionality. QuickLogic names phased-array radar, electronic warfare, wireless infrastructure, satellite communications and imaging algorithms as applications for the expanded signal-processing capability.

Reliability gets its own addition. The optional Configuration Bit Health Monitor detects and corrects configuration-bit errors induced by single-event upsets (SEUs) while the eFPGA user design is active. That is aimed at systems where configuration integrity must be maintained in near real time.

So what, concretely? Teams building compute-intensive or high-reliability SoCs could fit larger programmable-logic fabrics and specialized signal processing into the chip, then update selected hardware functions after manufacture. QuickLogic describes the underlying technology as silicon-proven.