UltraRISC shows UR-CP400 RISC-V core on FPGA prototype

At the sixth RISC-V Summit China, held in Shenzhen from October 18 to 20, the Shanghai company UltraRISC did not bring a chip to sell. It brought a processor core design, and a working FPGA prototype system to show it at its booth. An FPGA is a reprogrammable chip that can stand in for a finished processor during early testing.

UR-CP400 is a core IP, a design that UltraRISC licenses to chip designers, who build it into their own processors. UltraRISC also uses its cores in its own CPU products. Its architecture follows the RVA23 profile, a RISC-V standard that defines the features mainstream operating systems and software expect, and it supports version 1.0 of the RISC-V vector extension, the part of the instruction set that processes many data values at once. The microarchitecture is out-of-order with 8-wide issue and a 14-stage pipeline, which describes how many instructions the core can start in a single cycle and how its work is divided along the way.

The headline figure is a SPECint_base2006 score above 22 per GHz. SPECint is a standard benchmark for integer computing, and per GHz means the score per unit of clock speed. The number comes from the FPGA configuration, not from finished silicon, and the company does not give production clock speeds. For comparison, UltraRISC rates UR-CP100, the core inside its eight-core UR-DP1000 desktop CPU, at 10.4 per GHz on single-core SPECint2006. If the new figure holds in a real chip, UR-CP400 would more than double per-clock integer performance over that generation.

For the companies that license the core, the change is about what they can build, and when. UltraRISC says UR-CP400 adds virtualization enhancements for multi-layer cloud environments, is designed to support server CPU platforms, and includes hardware optimizations for agentic AI workloads, although it did not detail those AI-specific changes. Delivery to customers is planned for the first quarter of 2027, which means chip designers who want to use it in server or AI products would be working on their own implementations until then.

UltraRISC is not alone at the summit. Several companies used the event to show server-class and automotive RISC-V cores, and the company's own systems demonstrated edge AI, multi-node cluster and virtualization setups built on UR-DP1000. Every performance figure remains the company's claim, not an independent test result.